The present invention relates to a method for fabricating a semiconductor device, and more particularly, it relates to a technique to form a hole in a multi-layer insulating film composed of a lower insulating film made from a silicon nitride film, a silicon nitrided oxide film or a silicon carbide film and an upper insulating film made from a silicon oxide film.
In accordance with a recently increased degree of integration of semiconductor integrated circuit devices, there are increasing demands for refinement of semiconductor devices included in semiconductor integrated circuit devices, and therefore, a hole formed in an insulating film is required to have a high aspect ratio.
For example, in accordance with increased refinement of a MOS field effect transistor included in a semiconductor integrated circuit device, a capacitor used in a DRAM is also required to be refined. Accordingly, a stacked memory device in which a memory cell is disposed on a word line has become a leading memory device.
Now, a general stacked memory device will be described with reference to FIG. 5.
As shown in FIG. 5, a word line (gate electrode) 11 of a polysilicon film is formed on a semiconductor substrate 10 of a silicon substrate in which impurity diffusion layers 10a and 10b working as the source and the drain are formed, and a first interlayer insulating film 12 is deposited so as to cover the word line 11. A first contact 13 of a polysilicon film with its lower end connected to one impurity diffusion layer 10a is buried in the first interlayer insulating film 12.
A first insulating film 14 of, for example, a silicon nitride film working as an etching stopper film is deposited on the first interlayer insulating film 12, and a capacitor including a storage electrode 15, a capacitor dielectric film 16 and a plate electrode 17 is provided on the first interlayer insulating film 12. A second interlayer insulating film 18 is deposited on the first insulating film 14 so as to cover the capacitor. The upper end of the first contact 13 is connected to the storage electrode 15.
A second contact 19 with its lower end connected to the other impurity diffusion layer 10b is buried in the first interlayer insulating film 12, the first insulating film 14 and the second interlayer insulating film 18. A bit line 20 is provided on the second interlayer insulating film 18 so as to be connected to the upper end of the second contact 19.
Next, a conventional method for fabricating a stacked memory cell will be described. Beforehand, etching systems used in the conventional method for fabricating a stacked memory cell will be described with reference to FIGS. 9A and 9B.
FIG. 9A shows a rough cross-sectional structure of an inductively coupled plasma (ICP) etching system, that is, a high density plasma etching system. A lower electrode (sample table) 31 is provided in a lower portion of a chamber 30, and a semiconductor substrate 32 to be etched is held on the lower electrode 31. An induction coil 33 is provided on the outer face of the chamber 30, and RF power of 2.0 MHz is applied to the induction coil 33 by a first RF power supply 34. Also, RF power of 1.8 MHz is applied to the lower electrode 31 by a second RF power supply 35.
FIG. 9B shows a rough cross-sectional structure of a diode parallel plate RIE system, that is, a low density plasma etching system. A lower electrode (sample table) 41 is provided in a lower portion of a chamber 40, and a semiconductor substrate 42 to be etched is held on the lower electrode 41. RF power of 13.5 MHz is applied to the lower electrode 41 by an RF power supply 43. Also, an upper electrode 44 is provided in an upper portion of the chamber 40, and the upper electrode 44 is grounded.
Now, the conventional method for fabricating a memory cell by using the two kinds of etching systems of FIGS. 9A and 9B will be described with reference to FIGS. 6A through 6D, 7A through 7D and 8A through 8D.
First, as shown in FIG. 6A, after forming a word line 11 on a semiconductor substrate 10, a first interlayer insulating film 12 is deposited on the semiconductor substrate 10 so as to cover the word line 11. Thereafter, a first contact 13 of a polysilicon film is buried in the first interlayer insulating film 12 so as to be connected to one impurity diffusion layer 10a at its lower end.
Next, a first insulating film 14 of, for example, a silicon nitride film working as an etching stopper film and a second insulating film 21 of, for example, a silicon oxide film are successively deposited on the first interlayer insulating film 12.
Then, as shown in FIG. 6B, after an anti-reflection film 22 of an organic film is formed on the second insulating film 21, a first resist pattern 23 having a hole opening 23a is formed on the anti-reflection film 22.
Subsequently, by using the inductively coupled plasma etching system of FIG. 9A, the anti-reflection film 22 and the second insulating film 21 are successively etched with the first resist pattern 23 used as a mask, so as to form an upper hole 24a in the second insulating film 21 as shown in FIG. 6C.
The etching conditions for this etching are as follows: The pressure within the chamber 30 is set to 1.33 Pa; RF power (coil power) of 2700 W is applied to the induction coil 33 by the first RF power supply 34; and RF power (bias power) of 1300 W is applied to the lower electrode 31 by the second RF power supply 35.
In the etching of the anti-reflection film 22, a first etching gas of a mixture of a C2F6 gas (with a flow rate of 40 ml/min. (standard condition)) and an O2 gas (with a flow rate of 5 ml/min. (standard condition)) is introduced into the chamber 30. In the etching of the second insulating film 21, a second etching gas of a mixture of a C2F6 gas (with a flow rate of 40 ml/min. (standard condition)) and an O2 gas (with a flow rate of 2 ml/min. (standard condition)) is introduced into the chamber 30. Thus, the anti-reflection film 22 and the second insulating film 21 can be successively etched, and the etching can be definitely ended on the top face of the first insulating film 14.
Next, as shown in FIG. 6D, the resist pattern 23 and the anti-reflection film 22 are removed by ashing using oxygen plasma, and the resultant substrate is cleaned.
Thereafter, by using the diode parallel plate RIE system of FIG. 9B, the first insulating film 14 is etched by using, as a mask, the second insulating film 21 in which the upper hole 24a has been formed (namely, the patterned second insulating film) as shown in FIG. 7A, so as to form a lower hole 24b in the first insulating film 14. Then, etching residues are removed by the ashing. Thus, a hole 24 composed of the upper hole 24a and the lower hole 24b is formed.
The etching conditions for the etching of the first insulating film 14 are as follows: The pressure within the chamber 40 is set to 5 Pa; RF power of 600 W is applied to the lower electrode 41 by the RF power supply 43; and a third etching gas of a mixture of a CHF3 gas (with a flow rate of 110 ml/min. (standard condition)) and an O2 gas (with a flow rate of 12 ml/min. (standard condition)) is introduced into the chamber 40.
Also, the conditions for the ashing are as follows: The pressure within the chamber 40 is set to 133 Pa; RF power of 100 W is applied to the lower electrode 41 by the RF power supply 43; and a fourth etching gas of a mixture of a CF4 gas (with a flow rate of 100 ml/min. (standard condition)) and an O2 gas (with a flow rate of 100 ml/min. (standard condition)) is introduced into the chamber 40.
Next, as shown in FIG. 7B, a first polysilicon film 15A doped with, for example, phosphorus is deposited on the top face of the second insulating film 21 and on the wall and the bottom of the hole 24. Thereafter, a second resist pattern 24 is formed on the first polysilicon film 15A as shown in FIG. 7C.
Then, as shown in FIG. 7D, the second resist pattern 24 is etched back, so that a storage electrode forming region (corresponding to a portion present within the hole 24) of the second resist pattern 24 can remain. In other words, a portion of the first polysilicon film 15A present on the second insulating film 21 is exposed. This procedure is performed in order to protect a portion of the first polysilicon film 15A to be formed into a storage electrode in subsequently performed etching of the first polysilicon film 15A.
Next, as shown in FIG. 8A, the first polysilicon film 15A is etched by using the second resist pattern 24 as a mask, so as to form a storage electrode 15 in a bottomed cylindrical shape (with a U-shaped cross-section) from the first polysilicon film 15A. Thereafter, the second insulating film 21 and the second resist pattern 24 are removed by a vapor HF treatment, so as to expose the storage electrode 15 as shown in FIG. 8B.
Then, as shown in FIG. 8C, for example, a silicon nitrided oxide film 16A and a second polysilicon film 17A doped with, for example, phosphorus are successively deposited over the storage electrode 15 and the first insulating film 14. Thereafter, the second polysilicon film 17A, the silicon nitrided oxide film 16A and the first insulating film 14 are patterned, thereby forming a plate electrode 17 from the second polysilicon film 17A and a capacitor dielectric film 16 from the silicon nitrided oxide film 16A as shown in FIG. 8D.
Subsequently, although not shown in the drawings, a second interlayer insulating film 18, a second contact 19 and a bit line 20 are formed, resulting in completing the semiconductor device of FIG. 5.
In the aforementioned stacked memory device, the capacitance of the capacitor is determined depending upon the area of a portion where the storage electrode 15 opposes the plate electrode 17, namely, the height of the storage electrode 15. The height of the storage electrode 15 depends upon the depth of the hole 24. Accordingly, in order to attain constant capacitance of the capacitor, it is very significant to control the depth of the hole 24 to be constant.
Therefore, the first insulating film 14 working as an etching stopper film in the etching of the second insulating film 21 is formed below the second insulating film 21. However, since the first insulating film 14 is present below the second insulating film 21, it is necessary, for forming the hole 24, to etch the first insulating film 14 in addition to the second insulating film 21.
In the etching of the second insulating film 21, the second etching gas of a mixture of a C2F6 gas and an O2 gas is introduced into the chamber 30 of the inductively coupled plasma etching system, so as to generate high density plasma to be used for the etching.
In the etching of the first insulating film 14, the third etching gas of a mixture of a CHF3 gas and an O2 gas is introduced into the chamber 40 of the diode parallel plate RIE system, so as to generate low density plasma to be used for the etching.
The reasons why the different etching systems are thus used in the etching of the second insulating film 21 and in the etching of the first insulating film 14 will now be described.
The first reason is as follows: Since the second insulating film 21 has a comparatively large thickness, the etching time is too long if it is etched by using low density plasma. Accordingly, the second insulating film 21 is etched preferably by using high density plasma. In contrast, the first insulating film 14 has a comparatively small thickness. Therefore, if it is etched by using high density plasma, the etching rate is varied in the substrate plane, and hence, the depth of the hole 24 is varied and the etching end point is difficult to detect. Accordingly, the first insulating film 14 is etched preferably by using low density plasma.
The second reason is as follows: Since the second insulating film 21 is made from a silicon oxide film, it is necessary to use the etching gas of a mixture of a C2F6 gas and an O2 gas in the etching of the second insulating film 21. On the other hand, since the first insulating film 14 is made from a silicon nitride film, it is necessary to use the etching gas of a mixture of a CHF3 gas and an O2 gas in the etching of the first insulating film 14. Thus, it is necessary to change the etching gas between the etching of the second insulating film 21 and the etching of the first insulating film 14.
For these reasons, the different etching systems are used in the etching of the second insulating film 21 and the etching of the first insulating film 14. However, the use of the different etching systems increases the number of procedures and also largely increases the time required for forming a hole (turn around time; TAT).
Also in the case where the first insulating film 14 is made from a silicon nitrided oxide film or a silicon carbide film instead of a silicon nitride film, the same problems arise.